Intel's PowerVia technology is a major innovation in traditional chip power supply methods and is expected to be mass-produced on the Intel 20A process node in the first half of 2024. This technology is regarded as an important continuation of Moore's Law. Its development process is carried out independently from RibbonFET transistors to ensure that PowerVia can be effectively used in Intel 20A and 18A process chip production. Through extensive testing and debugging of PowerVia on internal test nodes, Intel has confirmed its significant role in improving chip efficiency. The unit utilization rate exceeds 90%, and it can significantly promote transistor shrinkage technology and help chip design companies improve their products. performance and energy efficiency.
Intel believes that PowerVia technology is another milestone after FinFET. While RibbonFET may not have an absolute advantage over competing GAAFET technologies, PowerVia's lead is clear. The industry does not expect TSMC to deploy similar technology before N2P nodes in late 2026 or early 2027. PowerVia is juxtaposed with Intel's past technological innovations such as strained silicon, high-K metal gates and FinFET transistors, reflecting Intel's continued leadership in chip technology innovation.
It is worth mentioning that the launch of Intel's 20A and 18A process nodes will not only serve the advancement of Intel's own products, but will also have a profound impact on the entire chip industry and Intel's foundry services. This marks Intel's official arrival of the angstrom era and opens a new chapter in chip technology.
Backside power supply network (BS-PDN), as one of the core technologies of PowerVia, has quietly emerged in the chip manufacturing industry similar to EUV technology, and is regarded as the basis for continuing to promote the development of finer process nodes. From the earliest stages of chip manufacturing, the construction of the power delivery network requires precise control, starting from etching the bottom layer of the transistor to the power supply on the top layer. This process requires the support of high-precision tools such as EUV and multiple exposure technology. It is this complex and precise construction that makes chip manufacturing an expensive and complicated process, but it is also the key to improving chip performance and efficiency.
On this basis, through the construction of multiple metal layers, electrons can be effectively transmitted between transistors to provide the required power and signals to various parts of the chip. Intel likens the process to making pizza, and while it may sound a bit simplistic, the metaphor vividly depicts the complexity of chip manufacturing. As technology advances, modern high-performance processors often contain as many as 10 to 20 metal layers, and once the chip is manufactured, the chip is often flipped over so that the power and data interfaces are on the bottom of the chip and the transistors are on top. . The advantage of this flip-chip design is that it is easier to debug and cool the chip, but it also brings many challenges to the front-end power supply.
PowerVia was introduced to address these challenges. By separating the signal and power transmission networks and building the power supply network on the back of the chip, PowerVia greatly simplifies the structure of the chip and makes it possible to improve chip performance. The direct benefit of this backside power supply method is that it not only relaxes the design rules of the metal layer and improves the degree of design freedom, but also slows down the IR Droop effect, improves the power transmission efficiency of the chip, eliminates interference, and thus solves the problem of data The interconnection bottleneck problem that has plagued the industry for a decade.
Of course, the implementation of PowerVia technology also faces its own challenges. Since the transistor layer is located roughly in the middle of the chip rather than at the end, traditional debugging tools cannot directly access the transistor layer for testing. Now there are about 15 layers of signal lines between the transistor layer and the heat dissipation layer. This challenge, while daunting, is not insurmountable. Intel successfully verified the effectiveness of these debugging processes by designing some controllable defects and using its own PowerVia debugging tool. At the same time, the technology to build the power layer on the back of the chip is also unprecedented. It increases the complexity of the manufacturing process and the possibility of errors. However, Intel has effectively improved the stability and reliability of the manufacturing process by using carrier wafers and TSV technology. .
Finally, Intel confirmed the success of PowerVia technology through a test chip code-named "Blue Sky Creek." Although PowerVia has higher technical implementation risks, by combining it with the Intel 4 process and leveraging EUV technology, Intel has demonstrated the significant advantages of PowerVia in improving unit utilization, reducing platform voltage, and increasing frequency efficiency, while also Demonstrates its good heat dissipation characteristics. This series of test results not only proves the feasibility of PowerVia technology, but also demonstrates its huge potential in future chip technology advancements.